Cadence Design Systems, Inc. has released an hotfix 02 for Cadence ASI 6.64, it's technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance.
Increases in IC speed, faster data transmission rates, smaller geometries, and an emphasis on optimization have made power and signal integrity issues tightly connected. To address these issues, designers need advanced power integrity and power-aware signal integrity tools. This level of technology allows designers to see the complete picture and achieve signoff-level verification through their analysis. Mistakes are not an option on projects this advanced, that's why designers choose proven Sigrity solutions, from Cadence.
By adopting Sigrity solutions, designers can perform three major tasks of the design verification process:
- Analyze the complete power delivery system across chips, packages, and boards.
- Perform system-level signal integrity (SI) analysis, including simultaneous switching noise analysis of high-speed signal transmissions.
- Utilize the advanced physical design tools for single and multi-chip packages, state-of-the-art 3D packages, and systems-in-package (SiPs).
There are four product options that run on top of Allegro Sigrity Base products, which combine existing Sigrity tools and include CAD translators to support PCB and Package designs from all of the major vendors. The option products are:
- Power Aware SI: Includes layout-based TD and FD simulation with or without ideal power, system-level simulation of parallel buses, and supporting tools for model conversion, extraction, and correction. (Option for SI Base)
- Serial Link SI: Includes all of the modeling and simulation capabilities need for system-level channel analysis. (Option for SI Base)
- Package Assessment and Model Extraction: Includes hybrid and 3D solvers, packages electrical assessment, and DC power analysis. (Option for SI Base or PI Base)
- Power Integrity Signoff and Optimization: Includes AC and DC sign-off analysis for PI and pre- and post-layout decoupling capacitor optimization for PI and EMI. (Option for PI Base) |
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