The software developer Mentor Graphics, is pleased to announce the availability of HDL Designer Series (HDS) 2019.4 is a powerful HDL-based environment used by individual engineers and engineering teams worldwide to analyze, create and manage complex FPGA and ASIC designs.

What’s New in HDL Designer Series 2019.4

Summary

SVAssistant
— High Level Block Diagram Visualization
— Visualizer Integration
— Multiple Simulation Configuration
— SystemVerilog performance improvements
– Scalability Mode
— SystemVerilog Find References
HDL Designer
— Simplified Vivado Integration Flow
DesignChecker
— General bug fixing
Quality
— >50 Defects & Enhancements Resolved