Cadence Design Systems, Inc., the leader in global electronic design innovation, has presented 15.12 version of Encounter Test, is a key technology of the Cadence Encounter digital IC design platform.
Cadence Encounter Test provides a comprehensive methodology for 3D-IC design-for-test and automatic test pattern generation that includes a DfT architecture that controls and observes an individual die from the chip I/Os, different test modes to control application of tests up and down the stack, and interconnect tests to detect through-silicon via defects. |