Mentor, a Siemens business, has unveiled QuestaSim 10.6c, is part of the Questa Advanced Functional Verification Platform and is the latest tool in Mentor Graphics tool suite for Functional Verification. New Features Contained in this Release: - Improved SystemVerilog/Verilog/VHDL performance and optimizations
- Improved profiling and capacity reporting, capstats tools
- Improved Gate Level performance and delay model support
- Gate Level new find loop feature
- Questa Fast Dumping (QFD) support for SAIF, TCL, UVM backdoor
- Code Coverage Adaptive Exclusions Support |
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